The present invention relates to integrated circuit (chip) design, and more specifically, to a technology mapping phase of a logical chip design.
Computer-aided design (CAD) tools aid in the design of circuits that will ultimately be implemented as semiconductor devices. The process of converting the logical (circuit) design to the physical realization of the design is referred to as synthesis and generally results in a gate-level placed netlist (list of connections). Within the logical design process, technology-independent logic synthesis is followed by technology mapping with standard cell library elements. This technology mapping is followed by post-technology-mapping synthesis optimization. At this stage, some of the decisions made in the technology mapping phase may be found to require rework. That is, when the technology mapping that is done with standard cell library elements is unaware of physical constraints on design, decisions made in the technology mapping phase may have to be corrected to account for physical constraints.